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<a href="#define-members">Macros</a> &#124;
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<div class="title">xgpiops_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gae9716887ddbdd1ac6093380b90d0eb57"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#gae9716887ddbdd1ac6093380b90d0eb57">XGPIOPS_HW_H</a></td></tr>
<tr class="memdesc:gae9716887ddbdd1ac6093380b90d0eb57"><td class="mdescLeft">&#160;</td><td class="mdescRight">by using protection macros  <a href="group__gpiops.html#gae9716887ddbdd1ac6093380b90d0eb57">More...</a><br/></td></tr>
<tr class="separator:gae9716887ddbdd1ac6093380b90d0eb57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac021029c611041a62843fbf68caa22de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#gac021029c611041a62843fbf68caa22de">XGPIOPS_BYPM_MASK_OFFSET</a>&#160;&#160;&#160;(u32)0x40</td></tr>
<tr class="memdesc:gac021029c611041a62843fbf68caa22de"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask for backward support.  <a href="group__gpiops.html#gac021029c611041a62843fbf68caa22de">More...</a><br/></td></tr>
<tr class="separator:gac021029c611041a62843fbf68caa22de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d0720a82ffbc02f22a5a2483415687a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga4d0720a82ffbc02f22a5a2483415687a">XGPIOPS_PS_GPIO_BASEADDR</a>&#160;&#160;&#160;0xFF0B0000U</td></tr>
<tr class="memdesc:ga4d0720a82ffbc02f22a5a2483415687a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag for Base Address for PS_GPIO in Versal.  <a href="group__gpiops.html#ga4d0720a82ffbc02f22a5a2483415687a">More...</a><br/></td></tr>
<tr class="separator:ga4d0720a82ffbc02f22a5a2483415687a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7bd601d046958f33b4fcd879f4fd6e5d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga7bd601d046958f33b4fcd879f4fd6e5d">XGPIOPS_ZERO</a>&#160;&#160;&#160;0U</td></tr>
<tr class="memdesc:ga7bd601d046958f33b4fcd879f4fd6e5d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag for 0 Value.  <a href="group__gpiops.html#ga7bd601d046958f33b4fcd879f4fd6e5d">More...</a><br/></td></tr>
<tr class="separator:ga7bd601d046958f33b4fcd879f4fd6e5d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga39c1b071b7df6679f0d1450de2b3bb48"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga39c1b071b7df6679f0d1450de2b3bb48">XGPIOPS_ONE</a>&#160;&#160;&#160;1U</td></tr>
<tr class="memdesc:ga39c1b071b7df6679f0d1450de2b3bb48"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag for 1 Value.  <a href="group__gpiops.html#ga39c1b071b7df6679f0d1450de2b3bb48">More...</a><br/></td></tr>
<tr class="separator:ga39c1b071b7df6679f0d1450de2b3bb48"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2bbdd623677a2984b1d0eb497337f559"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga2bbdd623677a2984b1d0eb497337f559">XGPIOPS_TWO</a>&#160;&#160;&#160;2U</td></tr>
<tr class="memdesc:ga2bbdd623677a2984b1d0eb497337f559"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag for 2 Value.  <a href="group__gpiops.html#ga2bbdd623677a2984b1d0eb497337f559">More...</a><br/></td></tr>
<tr class="separator:ga2bbdd623677a2984b1d0eb497337f559"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae7e81604ed741912fbaf1dac2b17d90c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#gae7e81604ed741912fbaf1dac2b17d90c">XGPIOPS_THREE</a>&#160;&#160;&#160;3U</td></tr>
<tr class="memdesc:gae7e81604ed741912fbaf1dac2b17d90c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag for 3 Value.  <a href="group__gpiops.html#gae7e81604ed741912fbaf1dac2b17d90c">More...</a><br/></td></tr>
<tr class="separator:gae7e81604ed741912fbaf1dac2b17d90c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5e6bff389611d55cc6ca4d3f21a7e4d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga5e6bff389611d55cc6ca4d3f21a7e4d2">XGPIOPS_FOUR</a>&#160;&#160;&#160;4U</td></tr>
<tr class="memdesc:ga5e6bff389611d55cc6ca4d3f21a7e4d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag for 4 Value.  <a href="group__gpiops.html#ga5e6bff389611d55cc6ca4d3f21a7e4d2">More...</a><br/></td></tr>
<tr class="separator:ga5e6bff389611d55cc6ca4d3f21a7e4d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga720e46128be37b99f48c07ed2f8587b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga720e46128be37b99f48c07ed2f8587b3">XGPIOPS_SIX</a>&#160;&#160;&#160;6U</td></tr>
<tr class="memdesc:ga720e46128be37b99f48c07ed2f8587b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag for 6 Value.  <a href="group__gpiops.html#ga720e46128be37b99f48c07ed2f8587b3">More...</a><br/></td></tr>
<tr class="separator:ga720e46128be37b99f48c07ed2f8587b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaff08ac5be0729f046324cae2706aaf9a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#gaff08ac5be0729f046324cae2706aaf9a">XGpioPs_ReadReg</a>(BaseAddr, RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddr) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:gaff08ac5be0729f046324cae2706aaf9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the given register.  <a href="group__gpiops.html#gaff08ac5be0729f046324cae2706aaf9a">More...</a><br/></td></tr>
<tr class="separator:gaff08ac5be0729f046324cae2706aaf9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3ad586332c0958c5044450d735127337"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga3ad586332c0958c5044450d735127337">XGpioPs_WriteReg</a>(BaseAddr, RegOffset, Data)&#160;&#160;&#160;Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:ga3ad586332c0958c5044450d735127337"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes to the given register.  <a href="group__gpiops.html#ga3ad586332c0958c5044450d735127337">More...</a><br/></td></tr>
<tr class="separator:ga3ad586332c0958c5044450d735127337"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register offsets for the GPIO. Each register is 32 bits.</div></td></tr>
<tr class="memitem:ga05aff41166bea96304f2fa71e21362c4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga05aff41166bea96304f2fa71e21362c4">XGPIOPS_DATA_LSW_OFFSET</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga05aff41166bea96304f2fa71e21362c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask and Data Register LSW, WO.  <a href="group__gpiops.html#ga05aff41166bea96304f2fa71e21362c4">More...</a><br/></td></tr>
<tr class="separator:ga05aff41166bea96304f2fa71e21362c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga05b7d35cd223526d8861934f44232284"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga05b7d35cd223526d8861934f44232284">XGPIOPS_DATA_MSW_OFFSET</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga05b7d35cd223526d8861934f44232284"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask and Data Register MSW, WO.  <a href="group__gpiops.html#ga05b7d35cd223526d8861934f44232284">More...</a><br/></td></tr>
<tr class="separator:ga05b7d35cd223526d8861934f44232284"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d795f07c1e9e4bfcac2859112fbbd88"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga3d795f07c1e9e4bfcac2859112fbbd88">XGPIOPS_DATA_OFFSET</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga3d795f07c1e9e4bfcac2859112fbbd88"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Register, RW.  <a href="group__gpiops.html#ga3d795f07c1e9e4bfcac2859112fbbd88">More...</a><br/></td></tr>
<tr class="separator:ga3d795f07c1e9e4bfcac2859112fbbd88"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga29e4ebe4ad7fef5e1a1fe215f578d8a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga29e4ebe4ad7fef5e1a1fe215f578d8a8">XGPIOPS_DATA_RO_OFFSET</a>&#160;&#160;&#160;0x00000060U</td></tr>
<tr class="memdesc:ga29e4ebe4ad7fef5e1a1fe215f578d8a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Register - Input, RO.  <a href="group__gpiops.html#ga29e4ebe4ad7fef5e1a1fe215f578d8a8">More...</a><br/></td></tr>
<tr class="separator:ga29e4ebe4ad7fef5e1a1fe215f578d8a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee82145f62455e2928a5b8fe66553a40"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#gaee82145f62455e2928a5b8fe66553a40">XGPIOPS_DIRM_OFFSET</a>&#160;&#160;&#160;0x00000204U</td></tr>
<tr class="memdesc:gaee82145f62455e2928a5b8fe66553a40"><td class="mdescLeft">&#160;</td><td class="mdescRight">Direction Mode Register, RW.  <a href="group__gpiops.html#gaee82145f62455e2928a5b8fe66553a40">More...</a><br/></td></tr>
<tr class="separator:gaee82145f62455e2928a5b8fe66553a40"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga74dfb9103ef810106a70f8355e319004"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga74dfb9103ef810106a70f8355e319004">XGPIOPS_OUTEN_OFFSET</a>&#160;&#160;&#160;0x00000208U</td></tr>
<tr class="memdesc:ga74dfb9103ef810106a70f8355e319004"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Enable Register, RW.  <a href="group__gpiops.html#ga74dfb9103ef810106a70f8355e319004">More...</a><br/></td></tr>
<tr class="separator:ga74dfb9103ef810106a70f8355e319004"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga63ee987794c805429f6e0c34b62ae5b9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga63ee987794c805429f6e0c34b62ae5b9">XGPIOPS_INTMASK_OFFSET</a>&#160;&#160;&#160;0x0000020CU</td></tr>
<tr class="memdesc:ga63ee987794c805429f6e0c34b62ae5b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Mask Register, RO.  <a href="group__gpiops.html#ga63ee987794c805429f6e0c34b62ae5b9">More...</a><br/></td></tr>
<tr class="separator:ga63ee987794c805429f6e0c34b62ae5b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga090dab3e38b9493eb63a30c4cc9a9267"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga090dab3e38b9493eb63a30c4cc9a9267">XGPIOPS_INTEN_OFFSET</a>&#160;&#160;&#160;0x00000210U</td></tr>
<tr class="memdesc:ga090dab3e38b9493eb63a30c4cc9a9267"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable Register, WO.  <a href="group__gpiops.html#ga090dab3e38b9493eb63a30c4cc9a9267">More...</a><br/></td></tr>
<tr class="separator:ga090dab3e38b9493eb63a30c4cc9a9267"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga457b603b9dda39af3aad037e3fb7fe89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga457b603b9dda39af3aad037e3fb7fe89">XGPIOPS_INTDIS_OFFSET</a>&#160;&#160;&#160;0x00000214U</td></tr>
<tr class="memdesc:ga457b603b9dda39af3aad037e3fb7fe89"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Disable Register, WO.  <a href="group__gpiops.html#ga457b603b9dda39af3aad037e3fb7fe89">More...</a><br/></td></tr>
<tr class="separator:ga457b603b9dda39af3aad037e3fb7fe89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6eac2572743836b91aae65e35e2b4ff2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga6eac2572743836b91aae65e35e2b4ff2">XGPIOPS_INTSTS_OFFSET</a>&#160;&#160;&#160;0x00000218U</td></tr>
<tr class="memdesc:ga6eac2572743836b91aae65e35e2b4ff2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register, RO.  <a href="group__gpiops.html#ga6eac2572743836b91aae65e35e2b4ff2">More...</a><br/></td></tr>
<tr class="separator:ga6eac2572743836b91aae65e35e2b4ff2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad50a2feb73c4055285aa11d1de90c402"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#gad50a2feb73c4055285aa11d1de90c402">XGPIOPS_INTTYPE_OFFSET</a>&#160;&#160;&#160;0x0000021CU</td></tr>
<tr class="memdesc:gad50a2feb73c4055285aa11d1de90c402"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Type Register, RW.  <a href="group__gpiops.html#gad50a2feb73c4055285aa11d1de90c402">More...</a><br/></td></tr>
<tr class="separator:gad50a2feb73c4055285aa11d1de90c402"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafd48f3262cc46cf828f219edcdb08920"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#gafd48f3262cc46cf828f219edcdb08920">XGPIOPS_INTPOL_OFFSET</a>&#160;&#160;&#160;0x00000220U</td></tr>
<tr class="memdesc:gafd48f3262cc46cf828f219edcdb08920"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Polarity Register, RW.  <a href="group__gpiops.html#gafd48f3262cc46cf828f219edcdb08920">More...</a><br/></td></tr>
<tr class="separator:gafd48f3262cc46cf828f219edcdb08920"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ba60ac847a2c6ad66240cf1a849afba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga9ba60ac847a2c6ad66240cf1a849afba">XGPIOPS_INTANY_OFFSET</a>&#160;&#160;&#160;0x00000224U</td></tr>
<tr class="memdesc:ga9ba60ac847a2c6ad66240cf1a849afba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt On Any Register, RW.  <a href="group__gpiops.html#ga9ba60ac847a2c6ad66240cf1a849afba">More...</a><br/></td></tr>
<tr class="separator:ga9ba60ac847a2c6ad66240cf1a849afba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register offsets for each Bank.</div></td></tr>
<tr class="memitem:ga1a0e56e2d9952e68d3737707d7b29581"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga1a0e56e2d9952e68d3737707d7b29581">XGPIOPS_DATA_MASK_OFFSET</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga1a0e56e2d9952e68d3737707d7b29581"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data/Mask Registers offset.  <a href="group__gpiops.html#ga1a0e56e2d9952e68d3737707d7b29581">More...</a><br/></td></tr>
<tr class="separator:ga1a0e56e2d9952e68d3737707d7b29581"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2253433045676585190fa543860141d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga2253433045676585190fa543860141d5">XGPIOPS_DATA_BANK_OFFSET</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga2253433045676585190fa543860141d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Registers offset.  <a href="group__gpiops.html#ga2253433045676585190fa543860141d5">More...</a><br/></td></tr>
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<tr class="memitem:ga9ba138bbcd05d5e10978166741a8184b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga9ba138bbcd05d5e10978166741a8184b">XGPIOPS_REG_MASK_OFFSET</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga9ba138bbcd05d5e10978166741a8184b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Registers offset.  <a href="group__gpiops.html#ga9ba138bbcd05d5e10978166741a8184b">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Interrupt type reset values for each bank</div></td></tr>
<tr class="memitem:ga8c9a16d604addea8146e2672823f1dc4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga8c9a16d604addea8146e2672823f1dc4">XGPIOPS_INTTYPE_BANK0_RESET</a>&#160;&#160;&#160;0xFFFFFFFFU</td></tr>
<tr class="memdesc:ga8c9a16d604addea8146e2672823f1dc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Resets specific to Zynq.  <a href="group__gpiops.html#ga8c9a16d604addea8146e2672823f1dc4">More...</a><br/></td></tr>
<tr class="separator:ga8c9a16d604addea8146e2672823f1dc4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae7120883729ac7440f9bbc378f21422a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#gae7120883729ac7440f9bbc378f21422a">XGPIOPS_INTTYPE_BANK1_RESET</a>&#160;&#160;&#160;0x003FFFFFU</td></tr>
<tr class="memdesc:gae7120883729ac7440f9bbc378f21422a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Resets specific to Zynq.  <a href="group__gpiops.html#gae7120883729ac7440f9bbc378f21422a">More...</a><br/></td></tr>
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<tr class="memitem:ga8aa4d8c9862e1f3af162c56a42b2e5f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga8aa4d8c9862e1f3af162c56a42b2e5f2">XGPIOPS_INTTYPE_BANK2_RESET</a>&#160;&#160;&#160;0xFFFFFFFFU</td></tr>
<tr class="memdesc:ga8aa4d8c9862e1f3af162c56a42b2e5f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Resets specific to Zynq.  <a href="group__gpiops.html#ga8aa4d8c9862e1f3af162c56a42b2e5f2">More...</a><br/></td></tr>
<tr class="separator:ga8aa4d8c9862e1f3af162c56a42b2e5f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa809c9d03d6939520e98babf4361100"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#gafa809c9d03d6939520e98babf4361100">XGPIOPS_INTTYPE_BANK3_RESET</a>&#160;&#160;&#160;0xFFFFFFFFU</td></tr>
<tr class="memdesc:gafa809c9d03d6939520e98babf4361100"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset common to both platforms.  <a href="group__gpiops.html#gafa809c9d03d6939520e98babf4361100">More...</a><br/></td></tr>
<tr class="separator:gafa809c9d03d6939520e98babf4361100"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga514054481f5f916ee70f5d8ea40d926b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#ga514054481f5f916ee70f5d8ea40d926b">XGPIOPS_INTTYPE_BANK4_RESET</a>&#160;&#160;&#160;0xFFFFFFFFU</td></tr>
<tr class="memdesc:ga514054481f5f916ee70f5d8ea40d926b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Resets specific to Zynq Ultrascale+ MP.  <a href="group__gpiops.html#ga514054481f5f916ee70f5d8ea40d926b">More...</a><br/></td></tr>
<tr class="separator:ga514054481f5f916ee70f5d8ea40d926b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae5904f463885a5fda6141f578da35bea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#gae5904f463885a5fda6141f578da35bea">XGPIOPS_INTTYPE_BANK5_RESET</a>&#160;&#160;&#160;0xFFFFFFFFU</td></tr>
<tr class="memdesc:gae5904f463885a5fda6141f578da35bea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Resets specific to Zynq Ultrascale+ MP.  <a href="group__gpiops.html#gae5904f463885a5fda6141f578da35bea">More...</a><br/></td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gafc3c808cbcebdad62fd51dae3721d832"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops.html#gafc3c808cbcebdad62fd51dae3721d832">XGpioPs_ResetHw</a> (UINTPTR BaseAddress)</td></tr>
<tr class="memdesc:gafc3c808cbcebdad62fd51dae3721d832"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function resets the GPIO module by writing reset values to all registers.  <a href="group__gpiops.html#gafc3c808cbcebdad62fd51dae3721d832">More...</a><br/></td></tr>
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